View MAX97001EWP_4813285.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-5130; Rev 0; 1/10
TION_KIT EVALUA BLE VAILA A
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers
General Description
The MAX97001 mono audio subsystem combines a mono speaker amplifier with a stereo headphone amplifier and an analog DPST switch. The headphone and speaker amplifiers have independent volume control and on/off control. The 4 inputs are configurable as 2 differential inputs or 4 single-ended inputs. The entire subsystem is designed for maximum efficiency. The high-efficiency, 700mW, Class D speaker amplifier operates directly from the battery and consumes no more than 1FA in shutdown mode. The Class H headphone amplifier utilizes a dual-mode charge pump to maximize efficiency while outputting a groundreferenced signal that does not require output coupling capacitors. The speaker amplifier incorporates a distortion limiter to automatically reduce the volume level when excessive clipping occurs. This allows high gain for low-level signals without compromising the quality of large signals. All control is performed using the 2-wire I2C interface. The MAX97001 operates over the extended -40NC to +85NC temperature range, and is available in the 2mm x 2.5mm, 20-bump, WLP package (0.5mm pitch).
Features
S 2.7V_to_5.5V_Speaker_Supply_Voltage S 1.6V_to_2V_Headphone_Supply_Voltage S 700mW_Speaker_Output_(VPVDD_=_3.7V,_ZSPK_=_8 +_68H) S 37mW/Channel_Headphone_Output_(RHP_=_16I) S Low-Emission_Class_D_Amplifier S Efficient_Class_H_Headphone_Amplifier S Ground-Referenced_Headphone_Outputs S 2_Stereo_Single-Ended/Mono_Differential_Inputs S Integrated_Distortion_Limiter_(Speaker_Outputs) S Integrated_DPST_Analog_Switch S No_Clicks_and_Pops S TDMA_Noise_Free S 2mm_x_2.5mm,_20-Bump,_0.5mm_Pitch_WLP_ Package
MAX97001
Ordering Information
PART MAX97001EWP+ TEMP_RANGE -40NC to +85NC PIN-PACKAGE 20 WLP
Applications
Cell Phones Portable Multimedia Players
+Denotes a lead(Pb)-free/RoHS-compliant package.
Simplified Block Diagram
1.8V BATTERY I2C CONTROL
POWER SUPPLY STEREO/ MONO INPUT
MAX97001
VOLUME CLASS H AMPLIFIER CHARGE PUMP STEREO/ MONO INPUT LIMITER VOLUME CLASS D AMPLIFIER
BYPASS
________________________________________________________________ _Maxim Integrated Products_ _ 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers MAX97001
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Functional Diagram/Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Digital I/O Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C TIMING Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Class D Speaker Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Ultra-Low EMI Filterless Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Distortion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Headphone Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DirectDrive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Class H Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 I2 C Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 1. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 2. Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 3. Mixer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 4. Volume Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Distortion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 5. Distortion Limiter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers MAX97001
TABLE OF CONTENTS (CONTINUED)
Table 6. Power Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Charge-Pump Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 7. Charge-Pump Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 START and STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Early STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Write Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Read Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Filterless Class D Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 RF Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Optional Ferrite Bead Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Charge-Pump Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Charge-Pump Flying Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Charge-Pump Holding Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Supply Bypassing, Layout, and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 WLP Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers MAX97001
Functional Diagram/Typical Application Circuit
1.6V TO 2V 2.7V TO 5.5V
1F VDD B4 PVDD D4
0.1F
10F
MUX
0.47F OPTIONAL
PGAINA -6dB TO +18dB
BIAS
INADIFF
B1 BIAS 1F
INA1 C1
LPMODE
HPLVOL: -64dB TO +6dB PGAINA -6dB TO +18dB
HPVDD CLASS H 0/3dB HPLEN HPVSS HPVDD
HPRVOL: -64dB TO +6dB
A2 HPL
0.47F OPTIONAL
INA2 C2
+
HPLMIX
MIX
0.47F OPTIONAL
PGAINB -6dB TO +18dB
CLASS H 0/3dB HPREN HPVSS PVDD
A1 HPR
INB1 D1
INBDIFF
HPRMIX
SPKVOL: -30dB TO +20dB
MIX
C5 OUTP CLASS D +12dB SPKEN PGND THD LIMITER D5 OUTN
0.47F OPTIONAL
PGAINB -6dB TO +18dB
SPKMIX
INB2 D2
+
ANALOG SWITCHES
MIX
LMTEN
COM1 C3 COM2 C4 VDD SDA B2 SCL B3 I2C INTERFACE BYPEN VDD
MAX97001
D3 GND A4 C1P
CHARGE PUMP A5 C1N B5 HPVDD A3 HPVSS
4
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers
ABSOLUTE_MAXIMUM_RATINGS
(Voltages with respect to GND.) VDD, HPVDD ........................................................-0.3V to +2.2V PVDD ....................................................................-0.3V to +6.0V HPVSS ..................................................................-2.2V to +0.3V C1N ..................................... (HPVSS - 0.3V) to (HPVDD + 0.3V) C1P ...................................................... -0.3V to (HPVDD + 0.3V) HPL, HPR ............................ (HPVSS - 0.3V) to (HPVDD + 0.3V) INA1, INA2, INB1, INB2, BIAS .............................-0.3V to +6.0V SDA, SCL .............................................................-0.3V to +6.0V COM1, COM2, OUTP, OUTN .................-0.3V to (PVDD + 0.3V) Continuous Current In/Out of PVDD, GND, OUT_ ........ Q800mA Continuous Current In/Out of HPR, HPL, VDD.............. Q140mA Continuous Current In/Out of COM1, COM2 ................ Q150mA Continuous Input Current (all other pins) ........................ Q20mA Duration of OUT_ Short Circuit to GND or PVDD .....Continuous Duration of Short Circuit Between OUTP and OUTN ...................................................Continuous Duration of HP_ Short Circuit to GND or VDD ...........Continuous Continuous Power Dissipation (TA = +70NC) 20-Bump WLP Multilayer Board (derate 13mW/NC above +70NC)................................1040mW Junction Temperature .....................................................+150NC Operating Temperature Range .......................... -40NC to +85NC Storage Temperature Range............................ -65NC to +150NC Soldering Temperature (reflow) ......................................+260NC
MAX97001
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL_CHARACTERISTICS
(VDD = 1.8V, VPVDD = 3.7V, VGND = 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB, speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1FF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER Speaker Amplifier Supply Voltage Range Headphone Amplifier Supply Voltage Range SYMBOL PVDD VDD CONDITIONS Guaranteed by PSRR test Guaranteed by PSRR test Low-power headphone mode, TA = +25NC HP mode, TA = +25NC, stereo SE input on INA, INB disabled SPK mode, TA = +25NC mono differential Input on INB, INA disabled SPK + HP mode, TA = +25NC, stereo SE input on INA, INB disabled Shutdown Current ISHDN TA = +25NC, VSHDN = 0V IVDD IPVDD IVDD IPVDD IVDD IPVDD IVDD IPVDD IVDD + IPVDD VVDD = 0V, IPVDD <1 10 41.2 16 5.5 20.6 7.2 27 9.6 5 kI MIN 2.7 1.6 1.35 0.35 1.35 0.75 0.32 1.38 1.35 1.8 TYP MAX 5.5 2 1.85 0.55 1.85 1.15 0.6 2.2 1.85 2.7 8 FA mA UNITS V V
Quiecsent Supply Current
Turn-On Time
tON
Time from power-on to full operation, including soft-start Gain = -6dB, -3dB TA = +25NC, internal gain Gain = 0dB, 3dB, 6dB, 9dB Gain = +18dB
ms
Input Resistance
RIN
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers MAX97001
ELECTRICAL_CHARACTERISTICS_(continued)
(VDD = 1.8V, VPVDD = 3.7V, VGND = 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB, speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1FF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER Feedback Resistance SYMBOL RF Preamp = 0dB Maximum Input Signal Swing Preamp = +18dB Preamp = external gain f = 1kHz (differential input mode), gain = 0dB f = 1kHz (differential input mode), gain = 18dB IN__ inputs VBIAS TA = +25NC, SPKM = 1 TA = +25NC, SPKMIX = 0x01, IN_DIFF = 0 Peak voltage, TA = +25NC, A-weighted, 32 samples per second, volume at mute (Note 2) Into shutdown Out of shutdown VPVDD = 2.7V to 5.5V Power-Supply Rejection Ratio (Note 2) f = 217Hz, 200mVP-P ripple f = 1kHz, 200mVP-P ripple f = 20kHz, 200mVP-P ripple Output Power (Note 3) Total Harmonic Distortion Plus Noise THD+N P 1%, f = 1kHz, ZSPK = 8I + 68FH THD+N VPVDD = 4.2V VPVDD = 3.7V VPVDD = 3.3V 50 1.125 1.13 CONDITIONS TA = +25NC, external gain MIN 19 TYP 20 2.3 0.29 2.3 x RINEX/RF 55 dB 32 1.2 1.2 Q0.5 Q1.5 -70 dBV -70 77 73 dB 73 57 920 700 550 0.05 96 dB 96 250 Q20 11.5 12 1.5 12.5 kHz kHz dB A 0.6 % mW 1.275 1.27 Q4 V V VP-P MAX 21 UNITS kI
Common-Mode Rejection Ratio Input DC Voltage Bias Voltage SPEAKER_AMPLIFIER Output Offset Voltage
CMRR
VOS
mV
Click-and-Pop Level
KCP
PSRR
TA = +25NC
f = 1kHz, POUT = 360mW, TA = +25NC, RSPK = 8I A-weighted, SPKMIX = 0x03, referenced to 700mW IN_DIFF = 0 (single-ended) IN_DIFF = 1 (differential)
Signal-to-Noise Ratio
SNR
Oscillator Frequency Spread-Spectrum Bandwidth Gain Current Limit 6
fOSC
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers
ELECTRICAL_CHARACTERISTICS_(continued)
(VDD = 1.8V, VPVDD = 3.7V, VGND = 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB, speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1FF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER Efficiency Output Noise CHARGE_PUMP VHPL = VHPR = 0V, TA = +25NC Charge-Pump Frequency
MAX97001
SYMBOL E
CONDITIONS POUT = 600mW, f = 1kHz A-weighted, (SPKMIX = 0x01), IN_DIFF = 1, SPKVOL = -30dB
MIN
TYP 87 37
MAX
UNITS % FVRMS
80
83 665 500 VDD VDD/2 -VDD -VDD/2
85 kHz
VHPL = VHPR = 0.2V VHPL = VHPR = 0.5V VHPL, VHPR > VTH VHPL, VHPR < VTH VHPL, VHPR > VTH VHPL, VHPR < VTH Output voltage at which the charge pump switches between fast and slow clock Output voltage at which the charge pump switches modes, VOUT rising or falling Time it takes for the charge pump to transition from Invert to split mode Time it takes for the charge pump to transition from split to invert mode TA = +25NC, volume at mute TA = +25NC, HP_MIX = 0x1, IN_DIFF = 0 Peak voltage, TA = +25NC, A-weighted, 32 samples per second, volume at mute (Note 2) Into shutdown Out of shutdown VDD = 1.62V to 1.98V f = 217Hz, VRIPPLE = 200mVP-P 70 QVDD x 0.05 QVDD x 0.21
Positive Output Voltage Negative Output Voltage
VHPVDD VHPVSS VTH1 VTH2
V V QVDD x 0.13 QVDD x 0.3
Headphone Output Voltage Threshold
QVDD x 0.08 QVDD x 0.25 32 20
V
ms Fs
Mode Transition Timeouts
HEADPHONE_AMPLIFIERS Output Offset Voltage VOS Q0.15 Q0.5 -74 dBV -74 85 Q0.6 mV
Click-and-Pop Level
KCP
84 dB 80
Power-Supply Rejection Ratio (Note 2)
PSRR
TA = +25NC
f = 1kHz, VRIPPLE = 200mVP-P f = 20kHz, VRIPPLE = 200mVP-P
69
7
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers MAX97001
ELECTRICAL_CHARACTERISTICS_(continued)
(VDD = 1.8V, VPVDD = 3.7V, VGND = 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB, speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1FF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER Output Power Channel-to-Channel Gain Tracking Total Harmonic Distortion Plus Noise Signal-to-Noise Ratio Slew Rate Capacitive Drive Crosstalk ANALOG_SWITCH On-Resistance RON INC_ = 20mA, VCOM_ = 0V and PVDD, SWEN = 1 VDIFCOM_ = 2VP-P, VCMCOM_= PVDD/2, f = 1kHz, SWEN = 1, ZSPK = 8I + 68FH TA = +25NC TA = TMIN to TMAX 10I in series with each switch No series resistors 0.05 % 0.3 1.6 4 5.2 I THD+N SNR SR CL HPL to HPR, HPR to HPL, f = 20Hz to 20kHz SYMBOL POUT CONDITIONS THD+N = 1%, f = 1kHz RHP = 16I RHP = 32I MIN TYP 37 30 Q0.3 0.02 0.03 100 0.35 200 68 0.1 Q2.5 MAX UNITS mW % % dB V/Fs pF dB
TA = +25NC, HPL to HPR, HPLMIX = 0x01, HPRMIX = 0x02, IN_DIFF = 0 POUT = 10mW, f = 1kHz RHP = 32I RHP = 16I
A-weighted, RHP = 16I, HPLMIX = 0x01, HPRMIX = 0x02, IN_DIFF = 0
Total Harmonic Distortion Plus Noise
THD+N
Off-Isolation PREAMPLIFIER
SWEN = 0, COM1 and COM2 to GND = 50I, f = 10kHz, referred to signal applied to OUTP and OUTN PGAIN_ = 000 PGAIN_ = 001 PGAIN_ = 010 -6.5 -3.5 -0.5 2.5 5.5 8.5 17.5 5.5 -68 19 -31
90
dB
-6 -3 0 3 6 9 18 6 -64 20 -30
-5.5 -2.5 +0.5 3.5 6.5 9.5 18.5 6.5 -60 -21 -29 dB dB
Gain
PGAIN_ = 011 PGAIN_ = 100 PGAIN_ = 101 PGAIN_ = 110
VOLUME_CONTROL HP_VOL = 0x1F Volume Level HP_VOL = 0x00 SPKVOL = 0x3F SPKVOL = 0x00
8
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers
ELECTRICAL_CHARACTERISTICS_(continued)
(VDD = 1.8V, VPVDD = 3.7V, VGND = 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB, speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1FF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER Mute Attenuation Zero-Crossing Detection Timeout LIMITER Attack Time Release Time Constant THDT1 = 0 THDT1 = 1 1 1.4 2.8 ms s SYMBOL f = 1kHz CONDITIONS Speaker Headphone MIN TYP 100 110 100 MAX UNITS dB ms
MAX97001
DIGITAL_I/O_CHARACTERISTICS
(VPVDD = 3.7V, VGND = 0V. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER DIGITAL_INPUTS_(SDA,_SCL) Input Voltage High Input Voltage Low Input Hysteresis VIH VIL VHYS TA = +25NC ISINK = 3mA 200 10 1.0 0.4 0.75 x VDD 0.35 x VDD V V mV pF FA V SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Capacitance CIN Input Leakage Current IIN DIGITAL_OUTPUTS_(SDA_Open_Drain) Output Low Voltage VOL
9
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers MAX97001
I2C_TIMING_CHARACTERISTICS
(VPVDD = 3.7V, VGND = 0V. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER Serial-Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (REPEATED) START Condition SCL Pulse-Width Low SCL Pulse-Width High Setup Time for a REPEATED START Condition Data Hold Time Data Setup Time SDA and SCL Receiving Rise Time SDA and SCL Receiving Fall Time SDA Transmitting Fall Time Setup Time for STOP Condition Bus Capacitance Pulse Width of Suppressed Spike Note_1: Note_2: Note_3: Note_4: SYMBOL fSCL tBUF tHD,STA tLOW tHIGH tSU,STA tHD,DAT tSU,DAT tR tF tF tSU,STO CB tSP 0 (Note 4) (Note 4) (Note 4) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 0.6 400 50 300 300 300 900 TYP MAX 400 UNITS kHz Fs Fs Fs Fs Fs ns ns ns ns ns Fs pF ns
100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design. Amplifier inputs are AC-coupled to GND. Class D amplifier testing performed with a resistive load in series with an inductor to simulate an actual speaker load. CB is in pF.
START CONDITION SCL 1 28
CLOCK PULSE FOR ACKNOWLEDGMENT
9 NOT ACKNOWLEDGE
SDA ACKNOWLEDGE
Figure 1. I2C Interface Timing Diagram
10
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers
Typical Operating Characteristics
(VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = , RHP = . CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1F. TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX97001 toc01
MAX97001
SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
SPEAKER VOLUME ATTENUATION (dB)
SPEAKER VOLUME ATTENUATION vs. VOLUME CONTROL CODE
MAX97001 toc02
5
SUPPLY CURRENT (mA)
SHUTDOWN CURRENT (A)
4 3 2 1 0 2.5
SPEAKER ONLY INPUTS AC-COUPLED TO GND INPUT = INA VSDA = VSCL = 3.3V
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
INPUTS AC-COUPLED TO GND VSDA = VSCL = 3.3V
8I LOAD 20 10 0 -10 -20 -30 -40
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
10
20
30
40
50
60
70
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
VOLUME CONTROL CODE (NUMERIC)
HEADPHONE VOLUME ATTENUATION vs. HP_VOL CODE
MAX97001 toc04
THD+N vs. FREQUENCY
MAX97001 toc05
THD+N vs. FREQUENCY
VPVDD = 3.7V ZSPK = 4I + 33F POUT = 1000mW THD+N (%) 0.1
MAX97001 toc06
10 HEADPHONE VOLUME ATTENUATION (dB) 0 -10 -20 -30 -40 -50 -60 -70 0 5 10 15 20 25 HP_VOL CODE (NUMERIC) 30
RIGHT AND LEFT 32I LOAD
10
VPVDD = 3.7V ZSPK = 8I + 68F
10
1 THD+N (%) POUT = 600mW 0.1
1
0.01 POUT = 200mW 0.001
0.01
POUT =200mW
0.001 0.01 0.1 1 FREQUENCY (kHz) 10 100 0.01 0.1 1 FREQUENCY (kHz) 10 100
35
THD+N vs. FREQUENCY
MAX97001 toc07
THD+N vs. OUTPUT POWER
VPVDD = 5.0V ZSPK = 8I + 68F fIN = 6kHz THD+N (%)
THD+N (%)
MAX97001 toc08
THD+N vs. OUTPUT POWER
VPVDD = 5.0V ZSPK = 4I + 33F fIN = 6kHz 1 0.1 0.01 fIN = 1kHz
MAX97001 toc09
10
VPVDD = 3.7V ZSPK = 8I + 68F
100 10 1 0.1 0.01
100 10
1 THD+N (%)
0.1
SSM
fIN = 1kHz
0.01 FFM 0.001 0.01 0.1 1 FREQUENCY (kHz) 10 100
fIN = 100Hz 2000 2200 1800 0 200 400 600 800 1000 1200 1400 1600 2400 0.001
0.001 0
fIN = 100Hz 500 1000 1500 2000 2500 3000 3500 4000 POUT (mW)
POUT (mW)
11
MAX97001 toc03
6
4.0
30
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers MAX97001
Typical Operating Characteristics (continued)
(VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = , RHP = . CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1F. TA = +25C, unless otherwise noted.)
THD+N vs. OUTPUT POWER
MAX97001 toc10
THD+N vs. OUTPUT POWER
MAX97001 toc11
THD+N vs. OUTPUT POWER
VPVDD = 3.7V ZSPK = 8I + 68F fIN = 6kHz THD+N (%) 1 0.1 0.01 fIN = 1kHz
MAX97001 toc12
100 10 THD+N (%) 1 0.1 0.01 fIN = 100Hz 0.001 0 fIN = 1kHz VPVDD = 4.2V ZSPK = 8I + 68F fIN = 6kHz
100 10 THD+N (%) 1 0.1 0.01 fIN = 100Hz 0.001 fIN = 1kHz VPVDD = 4.2V ZSPK = 4I + 33F fIN = 6kHz
100 10
fIN = 100Hz 0.001 1500 POUT (mW) 2000 2500 3000 0 200 400 600 POUT (mW) 800 1000 1200
200 400 600 800 1000 1200 1400 1600 POUT (mW)
0
500
1000
THD+N vs. OUTPUT POWER
MAX97001 toc13
EFFICIENCY vs. OUTPUT POWER
MAX97001 toc14
EFFICIENCY vs. OUTPUT POWER
90 80 EFFICIENCY (%) 70 60 50 40 30 20 ZSPK = 4I + 33F ZSPK = 8I + 68F
MAX97001 toc15
100 10 THD+N (%) 1 0.1 0.01 fIN = 100Hz 1800 200 400 600 0 1000 1200 1400 1600 0.001 fIN = 1kHz VPVDD = 3.7V ZSPK = 4I + 33F CIN = 1F fIN = 6kHz
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0
ZSPK = 8I + 68F
100
ZSPK = 4I + 33F
VPVDD = 5.0V fIN = 1kHz 0.5 1.0 1.5 2.0 2.5
10 0 0 0.2 0.4 0.6 0.8 1.0 POUT (W)
VPVDD = 3.7V fIN = 1kHz 1.2 1.4 1.6
2000
800
POUT (mW)
POUT (W)
OUTPUT POWER vs. SUPPLY VOLTAGE
MAX97001 toc16
OUTPUT POWER vs. SUPPLY VOLTAGE
MAX97001 toc17
OUTPUT POWER vs. LOAD RESISTANCE
1.8 1.6 OUTPUT POWER (W) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 THD+N = 1% VPVDD = 3.7V fIN = 1kHz ZSPK = LOAD + 68F THD+N = 10%
MAX97001 toc18
2.0 1.8 1.6 OUTPUT POWER (W) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2.5 3.0 3.5 4.0 4.5 5.0 THD+N = 1% THD+N = 10% fIN = 1kHz ZSPK = 8I + 68F
3.5 3.0 OUTPUT POWER (W) 2.5 2.0 1.5 1.0 0.5 0 THD+N = 1% THD+N = 10% fIN = 1kHz ZSPK = 4I + 33F
2.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1
10
100
1000
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
LOAD RESISTANCE (I)
12
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers
Typical Operating Characteristics (continued)
(VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = , RHP = . CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1F. TA = +25C, unless otherwise noted.)
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY
MAX97001 toc19
MAX97001
POWER-SUPPLY REJECTION RATIO vs. SUPPLY VOLTAGE
MAX97001 toc20
IN-BAND OUTPUT SPECTRUM
SSM fIN = 1kHz
MAX97001 toc21
0 -10 -20 -30 PSRR (dB) -50 -60 -70 -80 -90 -100 0.01 0.1 1 FREQUENCY (kHz) 10 -40 VRIPPLE = 200mVP-P VPVDD = 3.7V INPUTS AC-COUPLED TO GND
0 -20 -40 -60 -80 -100 2.5 3.0 3.5 4.0 4.5 5.0 VRIPPLE = 200mVP-P fIN = 1kHz INPUTS AC-COUPLED TO GND
0 -20
AMPLITUDE (dBV)
-40 -60 -80 -100 -120
100
PSRR (dB)
5.5
0
5
10 FREQUENCY (kHz)
15
20
SUPPLY VOLTAGE (V)
IN-BAND OUTPUT SPECTRUM
FFM fIN = 1kHz
MAX97001 toc22
WIDEBAND OUTPUT SPECTRUM
RBW = 100Hz FFM
MAX97001 toc23
0 -20
AMPLITUDE (dBV)
0 -20 OUTPUT AMPLITUDE (dBV) -40 -60 -80 -100 -120
-40 -60 -80 -100 -120 0 5 10 FREQUENCY (kHz) 15 20
0.1
1
10 FREQUENCY (MHz)
100
1000
WIDEBAND OUTPUT SPECTRUM
-10 OUTPUT AMPLITUDE (dBV) -20 -30 -40 -50 -60 -70 -80 -90 -100 0.1 1 10 FREQUENCY (MHz) 100 1000
SOFTWARE SHUTDOWN RESPONSE
MAX97001 toc25 MAX97001 toc24
0
RBW = 100Hz SSM
SDA 2V/div
SPKR OUTPUT 200mA/div
1ms/div
13
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers MAX97001
Typical Operating Characteristics (continued)
(VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = , RHP = . CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1F. TA = +25C, unless otherwise noted.)
SOFTWARE TURN-ON RESPONSE
MAX97001 toc26
THD+N vs. FREQUENCY
MAX97001 toc27
THD+N vs. FREQUENCY
RLOAD = 16I
MAX97001 toc28
10
RLOAD = 32I
10
SDA 2V/div THD+N (%)
1
1 THD+N (%)
POUT = 30mW
0.1
POUT = 20mW
0.1
SPKR OUTPUT 200mA/div
0.01 POUT = 5mW
0.01
POUT = 10mW
2ms/div
0.001 0.01 0.1 1 FREQUENCY (kHz) 10 100
0.001 0.01 0.1 1 FREQUENCY (kHz) 10 100
THD+N vs. OUTPUT POWER
MAX97001 toc29
THD+N vs. OUTPUT POWER
RLOAD = 16I fIN = 6kHz fIN = 100Hz THD+N (%) 0.1
MAX97001 toc30
10
RLOAD = 32I
10
1 THD+N (%)
fIN = 6kHz
1
0.1
0.01 fIN = 1kHz 0.001 0 5 10 15 20 25 30 35 40 OUTPUT POWER (mW) fIN = 100Hz
0.01
fIN = 1kHz
0.001 0 10 20 30 40 50 60 70 OUTPUT POWER (mW)
POWER DISSIPATION vs. OUTPUT POWER
MAX97001 toc31
OUTPUT POWER vs. LOAD RESISTANCE
fIN = 1kHz
MAX97001 toc32
110 100 POWER DISSIPATION (mW) 90 80 70 60 50 40 30 20 10 0 0
fIN = 1kHz POUT = PHPL + PHPR RLOAD = 16I
250 200 OUTPUT POWER (mW)
THD+N = 10% 150 100 50 0
RLOAD = 32I
THD+N = 1%
20
40
60
80
100
120
140
1
10
100
1000
OUTPUT POWER (mW)
LOAD RESISTANCE (I)
14
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers
Typical Operating Characteristics (continued)
(VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = , RHP = . CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1F. TA = +25C, unless otherwise noted.)
OUTPUT POWER vs. LOAD RESISTANCE
MAX97001 toc33
MAX97001
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY
MAX97001 toc34
OUTPUT SPECTRUM
-20 AMPLITUDE (dBV) -40 -60 -80 -100 -120 RLOAD = 32I fIN = 1kHz
MAX97001 toc35
90 80 70 OUTPUT POWER (W) 60 C1 = C2 = C3 = 2.2F C1 = C2 = C3 = 1F
0 -20 -40 PSRR (dB) -60 -80 -100 -120 -140 VRIPPLE = 200mVP-P VDD = 1.8V INPUTS AC-COUPLED TO GND
0
50 40 30 20 10 0 1 10 100 1000 LOAD RESISTANCE (I) fIN = 1kHz THD+N = 1% MEASURED AT HPR ONLY
0.01
0.1
1 FREQUENCY (kHz)
10
100
-140 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (kHz)
OUTPUT SPECTRUM
MAX97001 toc36
CROSSTALK vs. FREQUENCY
-10 -20 CROSSTALK (dB) -30 -40 -50 -60 -70 LEFT TO RIGHT RIGHT TO LEFT RLOAD = 32I
MAX97001 toc37
0 -20
AMPLITUDE (dBV)
0
RLOAD = 16I fIN = 1kHz
-40 -60 -80 -100 -120 -140 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (kHz)
-80 -90 0.01 0.1 1 FREQUENCY (kHz) 10 100
COMMON-MODE REJECTION RATIO vs. FREQUENCY
RLOAD = 32I PREGAIN = +18dB -10 CROSSTALK (dB) -20 -30 -40 -50 -60 -70 0.01 0.1 1 FREQUENCY (kHz) 10 100 PREGAIN = +9dB PREGAIN = 0dB
MAX97001 toc38
SOFTWARE SHUTDOWN RESPONSE
MAX97001 toc39
0
SDA 2V/div
HPL/HPR 200mV/div
1ms/div
15
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers MAX97001
Typical Operating Characteristics (continued)
(VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = , RHP = . CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1F. TA = +25C, unless otherwise noted.)
SOFTWARE STARTUP RESPONSE
MAX97001 toc40
CLASS H OPERATION
MAX97001 toc41
HPVDD 1V/div SDA 2V/div 0V
HPL/HPR 200mV/div HPL/HPR 200mV/div
0V HPVSS 1V/div
2ms/div
10ms/div
THD+N vs. OUTPUT POWER
MAX97001 toc42
ON-RESISTANCE vs. VCOM
MAX97001 toc43
BYPASS SWITCH OFF-ISOLATION
MAX97001 toc44
10 RLOAD = 8I EXTERNAL CLASS AB CONNECTED DIRECTLY TO COM1 AND COMR f = 6kHz 0.1 f = 100Hz 0.01 f = 1kHz
3.5 3.0 2.5 RON (I) 2.0 1.5 1.0 0.5
INC = 20mA
0 -20 OFF-ISOLATION (dB) -40 -60 -80 -100 -120 0.01 0.1 1 FREQUENCY (kHz) 10
PVDD = 2.5V PVDD = 2.7V PVDD = 3.0V PVDD = 3.7V
1 THD+N (%)
PVDD = 5.0V
PVDD = 5.5V
0.001 0 10 20 30 40 50 60 70 80 OUTPUT POWER (mW)
0 0 1 2 3 VCOM (V) 4 5 6
100
16
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers
Pin Configuration
TOP VIEW (BUMP SIDE DOWN) 1 2 3 4 5
MAX97001
+ MAX97001
A HPR HPL HPVSS C1P C1N
B
BIAS
SDA
SCL
VDD
HPVDD
C
INA1
INA2
COM1
COM2
OUTP
D
INB1
INB2
GND
PVDD
OUTN
Pin Description
PIN A1 A2 A3 A4 A5 B1 B2 B3 B4 B5 C1 C2 C3 C4 C5 D1 D2 D3 D4 D5 NAME HPR HPL HPVSS C1P C1N BIAS SDA SCL VDD HPVDD INA1 INA2 COM1 COM2 OUTP INB1 INB2 GND PVDD OUTN Headphone Amplifier Left Output Headphone Amplifier Right Output Headphone Amplifier Negative Power Supply. Bypass with a 1FF capacitor to GND. Charge-Pump Flying Capacitor Positive Terminal. Connect a 1FF capacitor between C1P and C1N. Charge-Pump Flying Capacitor Negative Terminal. Connect a 1FF capacitor between C1P and C1N. Common-Mode Bias. Bypass to GND with a 1FF capacitor. Serial-Data Input/Output. Connect a pullup resistor from SDA to DVDD. Serial-Clock Input. Connect a pullup resistor from SCL to DVDD. Headphone Amplifier Supply. Bypass with a 1FF capacitor to GND. Headphone Amplifier Positive Power Supply. Bypass with a 1FF capacitor to GND. Input A1. Left input or negative input. Input A2. Right input or positive input. Positive Bypass Switch Input Negative Bypass Switch Input Positive Speaker Output Input B1. Left input or negative input. Input B2. Right input or positive input. Analog Ground Class D Power Supply. Bypass with a 1FF capacitor to GND. Negative Speaker Output FUNCTION
17
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers MAX97001
Detailed Description
The MAX97001 mono audio subsystem combines a mono speaker amplifier with a stereo headphone amplifier and an analog DPST switch. The high-efficiency, 700mW, Class D speaker amplifier operates directly from the battery and consumes no more than 1FA when in shutdown mode. The headphone amplifier utilizes a dual-mode charge pump and a Class H output stage to maximize efficiency while outputting a ground-referenced signal that does not require output-coupling capacitors. The headphone and speaker amplifiers have independent volume control and on/off control. The 4 inputs are configurable as 2 differential inputs or 4 single-ended inputs. All control is performed using the 2-wire I2C interface. The speaker amplifier incorporates a distortion limiter to automatically reduce the volume level when excessive clipping occurs. This allows high gain for low-level signals without compromising the quality of large signals. The MAX97001 signal path consists of flexible inputs, signal mixing, volume control, and output amplifiers (Figure 2). The inputs can be configured for singleended or differential signals (Figure 3). The internal preamplifiers feature programmable gain settings using internal resistors and an external gain setting using a trimmed internal feedback resistor. The external option allows any desired gain to be selected. Following preamplification, the input signals are mixed, volume adjusted, and routed to the headphone and speaker amplifiers based on the desired configuration. The MAX97001 features independent mixers for the left headphone, right headphone, and speaker paths. Each output can select any combination of any inputs. This allows for mixing two audio signals together and routing independent signals to the headphone and speaker amplifiers. If one of the inputs is not selected by either mixer, it is automatically powered down to save power. The MAX97001 Class D speaker amplifier utilizes active emissions limiting and spread-spectrum modulation to minimize the EMI radiated by the amplifier.
Mixers
Class D Speaker Amplifier
Signal Path
INA2 INA1
INPUT A -6dB TO +18dB MIXER AND MUX
-64dB TO +6dB
0/3dB
INB2 INB1
-64dB TO +6dB
0/3dB
INPUT B -6dB TO +18dB -30dB TO +20dB +12dB
Figure 2. Signal Path
18
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers MAX97001
STEREO SINGLE-ENDED
IN_2 (R) R
TO MIXER
IN_1 (L) L
DIFFERENTIAL
IN_2 (+)
IN_1 (-) TO MIXER
Figure 3. Differential and Stereo Single-Ended Input Configurations
19
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers MAX97001
Ultra-Low EMI Filterless Output Stage Traditional Class D amplifiers require the use of external LC filters or shielding in order to meet EN55022B electromagnetic-interference (EMI) regulation standards. Maxim's patented active emissions limiting edgerate control circuitry and spread-spectrum modulation reduces EMI emissions, while maintaining up to 87% efficiency. Maxim's patented spread-spectrum modulation mode flattens wideband spectral components, while proprietary techniques ensure that the cycle-to-cycle variation of the switching period does not degrade audio reproduction or efficiency. The MAX97001's spreadspectrum modulator randomly varies the switching frequency by Q20kHz around the center frequency (250kHz). Above 10MHz, the wideband spectrum looks like noise for EMI purposes (see Figure 4).
40 30 AMPLITUDE (dBV/m) 20 10 0 -10 30 60 80 100 120 140 160 180 200 220 240 260 280 300 FREQUENCY (MHz) 40 30 AMPLITUDE (dBV/m) 20 10 0 -10 300 350 400 450 500 550 600
650
700
750
800
850
900
950
1000
FREQUENCY (MHz)
Figure 4. EMI with 15cm of Speaker Cable
20
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers
Distortion Limiter The MAX97001 speaker amplifiers integrate a limiter to provide speaker protection and audio compression. When enabled, the limiter monitors the audio signal at the output of the Class D speaker amplifier and decreases the gain if the distortion exceeds the predefined threshold. The limiter automatically tracks the battery voltage to reduce the gain as the battery voltage drops. Figure 5 shows the typical output vs. input curves with and without the distortion limiter. The dotted line shows the maximum gain for a given distortion limit without the distortion limiter. The solid line shows how, with the distortion limiter enabled, the gain can be increased without exceeding the set distortion limit. When the limiter is enabled, selecting a high gain level results in peak signals being attenuated while low signals are left unchanged. This increases the perceived loudness without the harshness of a clipped waveform. The MAX97001 integrates a DPST analog audio switch that connects COM1 and COM2 to OUTP and OUTN, respectively. Unlike discrete solutions, the switch design reduces coupling of Class D switching noise to the COM_ inputs. This eliminates the need for a costly T-switch. Drive COM1 and COM2 with a low-impedance source to minimize noise on the pins. In applications that do not require the analog switch, leave COM1 and COM2 unconnected. When applying signal on COM1 and COM2, disable the Class D amplifier before closing the switch.
MAX97001
VOUT MAXIMUM THD+N LEVEL
VIN
Figure 5. Limiter Gain Curve
VDD
VDD/2
Analog Switch
GND CONVENTIONAL AMPLIFIER BIASING SCHEME +VDD
Headphone Amplifier
DirectDrive Traditional single-supply headphone amplifiers have outputs biased at a nominal DC voltage (typically half the supply). Large coupling capacitors are needed to block this DC bias from the headphone. Without these capacitors, a significant amount of DC current flows to the headphone, resulting in unnecessary power dissipation and possible damage to both headphone and headphone amplifier. Maxim's patented DirectDrive(R) architecture uses a charge pump to create an internal negative supply voltage. This allows the headphone outputs of the MAX97001 to be biased at GND while operating from a single supply (Figure 6). Without a DC component, there is no need for the large DC-blocking capacitors. Instead of two large (220FF, typ) capacitors, the MAX97001 charge pump requires two small ceramic capacitors, conserving board space, reducing cost, and improving the frequency response of the headphone amplifier.
SGND
-VDD DirectDrive AMPLIFIER BIASING SCHEME
Figure 6. Traditional Amplifier Output vs. MAX97001 DirectDrive Output
See the Output Power vs. Load Resistance graph in the Typical Operating Characteristics for details of the possible capacitor sizes. There is a low DC voltage on the amplifier outputs due to amplifier offset. However, the offset of the MAX97001 is typically Q0.6mV, which, when combined with a 32I load, results in less than 50FA of DC current flow to the headphones.
DirectDrive is a registered trademark of Maxim Integrated Products, Inc. 21
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers MAX97001
In addition to the cost and size disadvantages of the DC-blocking capacitors required by conventional headphone amplifiers, these capacitors limit the amplifier's low-frequency response and can distort the audio signal. Previous attempts at eliminating the outputcoupling capacitors involved biasing the headphone return (sleeve) to the DC-bias voltage of the headphone amplifiers. This method raises some issues: U The sleeve is typically grounded to the chassis. Using the midrail biasing approach, the sleeve must be isolated from system ground, complicating product design. U During an ESD strike, the amplifier's ESD structures are the only path to system ground. Thus, the amplifier must be able to withstand the full energy from an ESD strike. U When using the headphone jack as a line out to other equipment, the bias voltage on the sleeve may conflict with the ground potential from other equipment, resulting in possible damage to the amplifiers. Charge Pump The MAX97001's dual-mode charge pump generates both the positive and negative power supply for the headphone amplifier. To maximize effficiency, both the charge pump's switching frequency and output voltage change based on signal level. When the input signal level is less than 10% of VDD the switching frequency is reduced to a low rate. This minimizes switching losses in the charge pump. When the input signal exceeds 10% of VDD, the switching frequency increases to support the load current. For input signals below 25% of VDD, the charge pump generates Q(VDD/2) to minimize the voltage drop across the amplifier's power stage and thus improves efficiency. Input signals that exceed 25% of VDD cause the charge pump to output QVDD. The higher output voltage allows for full output power from the headphone amplifier. To prevent audible glitches when transitioning from the Q(VDD/2) output mode to the QVDD output mode, the charge pump transitions very quickly. This quick change draws significant current from VDD for the duration of the transition. The bypass capacitor on VDD supplies the required current and prevent droop on VDD. The charge pump's dynamic switching mode can be turned off through the I2C interface. The charge pump can then be forced to output either Q(VDD/2) or QVDD regardless of input signal level. Class H Operation A Class H amplifier uses a Class AB output stage with power supplies that are modulated by the output signal. In the case of the MAX97001, two nominal power-supply differentials of 1.8V (+0.9V to -0.9V) and 3.6V (+1.8V to -1.8V) are available from the charge pump. Figure 7 shows the operation of the output voltage dependent power supply. Low-Power Mode To minimize power consumption when using the headphone amplifier, enable the low-power mode. In this mode, the headphone mixers and volume control are bypassed and shutdown. The MAX97001 uses a slave address of 0x9A or 1001101R/W. The address is defined as the 7 most significant bits (MSBs) followed by the read/write bit. Set the read/ write bit to 1 to configure the MAX97001 to read mode. Set the read/write bit to 0 to configure the MAX97001 to write mode. The address is the first byte of information sent to the MAX97001 after the START (S) condition.
I2C Slave Address
1.8V 0.9V VTH_H OUTPUT VOLTAGE VTH_L -0.9V -1.8V HPVDD 32ms
HPVSS
32ms
Figure 7. Class H Operation
22
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers
I2C Registers Nine internal registers program the MAX97001. Table 1 lists all of the registers, their addresses, and power-onreset states. Register 0xFF indicates the device revision. Write zeros to all unused bits in the register table when updating the register, unless otherwise noted. Tables 2-7 describe each bit.
MAX97001
Table_1._Register_Map
REGISTER STATUS Input Gain Headphone Mixers Speaker Mixer Headphone Left Headphone Right Speaker Reserved Limiter Power Management Charge Pump REVISION_ID Rev ID REV 0xFF 0x00 R SHDN 0 0 ZCD HPGAIN FFM 0 INADIFF INBDIFF HPLMIX 0 SLEW 0 SPKM 0 THDCLP LPMODE 0 0 SPKEN 0 0 0 0 0 0 0 0 HPLM HPRM 0 PGAINA PGAINB HPRMIX SPKMIX HPLVOL HPRVOL SPKVOL 0 0 HPLEN 0 0 0 HPREN CPSEL 0 THDT1 BYPEN FIXED 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W B7 B6 B5 B4 B3 B2 B1 B0 ADDRESS DEFAULT R/W
23
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers MAX97001
Table_2._Input_Register
REGISTER BIT NAME DESCRIPTION Input_A_Differential_Mode. Configures the input A channel as either a mono differential signal (INA = INA2 - INA1) or as a stereo signal (INA1 = left, INA2 = right). 0 = Stereo single-ended 1 = Differential Input_B_Differential_Mode. Configures the input B channel as either a mono differential signal (INB = INB2 - INB1) or as a stereo signal (INB1 = left, INB2 = right). 0 = Stereo single-ended 1 = Differential Input_A_Preamp_Gain. Set the input gain to maximize output signal level for a given input signal range to improve the SNR of the system. PGAINA = 111 switches to a trimmed 20kI feedback resistor for external gain setting. VALUE LEVEL_(dB) 000 -6 001 -3 010 0 011 3dB 100 6 101 9 110 18 111 External Input_B_Preamp_Gain. Set the input gain to maximize output signal level for a given input signal range to improve the SNR of the system. PGAINB = 111 switches to a trimmed 20kI feedback resistor for external gain setting. VALUE LEVEL_(dB) 000 -6 001 -3 010 0 011 3 100 6 101 9 110 18 111 External
7
INADIFF
6
INBDIFF
5
4 0x00 3
PGAINA
2
1
PGAINB
0
24
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers
Mixers
MAX97001
Table_3._Mixer_Registers
REGISTER BIT 7 6 HPLMIX 5 4 0x01 3 2 HPRMIX 1 0 3 2 1 0 NAME DESCRIPTION Left_Headphone_Mixer. Selects which of the four inputs is routed to the left headphone output. VALUE INPUT 0000 No input 1xxx INA1 (disabled when INADIFF = 1) x1xx INA2 (select when INADIFF = 1) xx1x INB1 (disabled when INBDIFF = 1) xxx1 INB2 (select when INBDIFF = 1) Right_Headphone_Mixer. Selects which of the four inputs is routed to the right headphone output. VALUE INPUT 0000 No input 1xxx INA1 (disabled when INADIFF = 1) x1xx INA2 (select when INADIFF = 1) xx1x INB1 (disabled when INBDIFF = 1) xxx1 INB2 (select when INBDIFF = 1)
Speaker_Mixer. Selects which of the four inputs is routed to the speaker output. VALUE 0000 1xxx x1xx xx1x xxx1 INPUT No input INA1 (disabled when INADIFF = 1) INA2 (select when INADIFF = 1) INB1 (disabled when INBDIFF = 1) INB2 (select when INBDIFF = 1)
0x02
SPKMIX
25
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers MAX97001
Volume Control
Table_4._Volume_Control_Registers
REGISTER BIT NAME DESCRIPTION Zero-Crossing_Detection. Determines whether zero-crossing detection is used on all volume control changes to reduce clicks and pops. Disabling zero-crossing detection allows volume changes to occur immediately. 0 = Enabled 1 = Disabled Volume_Slewing._Determines whether volume slewing is used on all volume control changes to reduce clicks and pops. When enabled, volume changes cause the MAX97001 to ramp through intermediate volume settings whenever a change to the volume is made. If ZCD = 1, slewing occurs at a rate of 0.2ms per step. If ZCD = 0, slew time depends on the input signal. Write a 1 to this bit to disable slewing and implement volume changes immediately. This bit also activates soft-start at power-on and soft-stop and power-off. 0 = Enabled 1 = Disabled Left_Headphone_Mute 0 = Unmuted 1 = Muted Left_Headphone_Volume 0x03 4 VALUE 0x00 0x01 0x02 3 0x03 0x04 0x05 HPLVOL 2 0x06 0x07 0x08 0x09 0x0A 1 0x0B 0x0C 0x0D 0 0x0E 0x0F LEVEL_(dB) -64 -60 -56 -52 -48 -44 -40 -37 -34 -31 -28 -25 -22 -19 -16 -14 VALUE 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F LEVEL_(dB) -12 -10 -8 -6 -4 -2 -1 0 1 2 3 4 4.5 5 5.5 6
7
ZCD
6
SLEW
5
HPLM
26
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers
Table_4._Volume_Control_Registers_(continued)
REGISTER BIT 7 NAME HPGAIN DESCRIPTION Headphone_Gain. Controls the headphone amplifier gain. 0 = 0dB 1 = 3dB Right_Headphone_Mute 0 = Unmuted 1 = Muted Right_Headphone_Volume 4 VALUE 0x00 0x01 3 0x04 2 HPRVOL 0x02 0x03 0x04 0x05 0x06 0x07 0x08 1 0x09 0x0A 0x0B 0x0C 0 0x0D 0x0E 0x0F LEVEL_(dB) -64 -60 -56 -52 -48 -44 -40 -37 -34 -31 -28 -25 -22 -19 -16 -14 VALUE 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F LEVEL_(dB) -12 -10 -8 -6 -4 -2 -1 0 1 2 3 4 4.5 5 5.5 6
MAX97001
5
HPRM
27
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers MAX97001
Table_4._Volume_Control_Registers_(continued)
REGISTER BIT 7 NAME FFM DESCRIPTION Fixed-Frequency_Oscillation. Removes spread spectrum from the Class D oscillator. 0 = Spread-spectrum mode 1 = Fixed-frequency mode Speaker_Mute 0 = Unmuted 1 = Mute Speaker_Volume 5 VALUE 0x00-0x18 4 0x05 3 SPKVOL 2 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 1 0x22 0x23 0 0x24 0x25 LEVEL_(dB) -30 -26 -22 -18 -14 -12 -10 -8 -6 -4 -2 0 1 2 VALUE 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 LEVEL_(dB) 3 4 5 6 7 8 9 10 11 12 12.5 13 13.5 14 VALUE 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F LEVEL_ (dB) 14.5 15 15.5 16 16.5 17 17.5 18 18.5 19 19.5 20
6
SPKM
28
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers
Distortion Limiter
MAX97001
Table_5._Distortion_Limiter_Register
REGISTER BIT 7 NAME Distortion_Limit VALUE 0000 6 THDCLP 0x07 5 0001-1001 1010 1011 1100 1101 1110 4 1111 0000 0 THDT1 Distortion_Release_Time_Constant 0 = 1.4s 1 = 2.8s THD_LIMIT_(%) Disabled P4 P5 P6 P8 P 11 P 12 P 15 Disabled DESCRIPTION
Power Management
Table_6._Power_Management_Register
REGISTER BIT 7 NAME SHDN Software_Shutdown 0 = Device disabled 1 = Device enabled Low-Power_Headphone_Mode. Enables low-power headphone mode. When activated, this mode directly connects the selected channel to the headphone amplifiers, bypassing the mixers and the volume control. Additionally, low-power mode disables the speaker path. VALUE LIMIT_ 00 01 10 11 0x08 4 SPKEN Disabled INA (SE) Connected to the headphone output INB (SE) Connected to the headphone output INA (Diff) to HPL and INB (Diff) to HPR DESCRIPTION
6 LPMODE 5
Speaker_Amplifier_Enable 0 = Disabled 1 = Enabled Left_Headphone_Amplifier_Enable 0 = Disabled 1 = Enabled Right_Headphone_Amplifier_Enable 0 = Disabled 1 = Enabled Analog_Switch 0 = Open 1 = Closed 29
2
HPLEN
1
HPREN
0
BYPEN
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers MAX97001
Charge-Pump Control
Table_7._Charge-Pump_Control_Register
REGISTER BIT NAME DESCRIPTION Charge-Pump_Output_Select. Works with the FIXED to set Q1.8V or Q0.9V outputs on HPVDD and HPVSS. Ignored when FIXED = 0. 0 = Q1.8V on HPVDD/HPVSS 1 = Q0.9V on HPVDD/HPVSS Class_H_Mode. When enabled, this bit forces the charge pump to generate static power rails for HPVDD and HPVSS, instead of dynamically adjusting them based on output signal level. 0 = Class H mode 1 = Fixed-supply mode
1
CPSEL
0x09 0 FIXED
The MAX97001 features an I2C/SMBusK-compatible, 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the MAX97001 and the master at clock rates up to 400kHz. Figure 1 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. The master device writes data to the MAX97001 by transmitting the proper slave address followed by the register address and then the data word. Each transmit sequence is framed by a START or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted to the MAX97001 is 8 bits long and is followed by an acknowledge clock pulse. A master reading data from the MAX97001 transmits the proper slave address followed by a series of nine SCL pulses. The MAX97001 transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START or REPEATED START condition, a not acknowledge, and a STOP condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500I, is required on SDA. SCL operates only as an input. A pullup resistor, typically greater than 500I, is required on SCL if there are multiple masters on the bus, or if the single master has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX97001 from high-voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals.
SMBus is a trademark of Intel Corp. 30
I2C Serial Interface
Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 8). A START condition from the master signals the beginning of a transmission to the MAX97001. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition.
S SCL
Sr
P
SDA
Figure 8. START, STOP, and REPEATED START Conditions
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers
Early STOP Conditions The MAX97001 recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. Slave Address The slave address is defined as the seven most significant bits (MSBs) followed by the read/write bit. For the MAX97001 the 7 MSBs are 1001101. Setting the read/write bit to 1 (slave address = 0x9B) configures the MAX97001 for read mode. Setting the read/write bit to 0 (slave address = 0x9A) configures the MAX97001 for write mode. The address is the first byte of information sent to the MAX97001 after the START condition. Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the MAX97001 uses to handshake receipt each byte of data when in write mode (Figure 9). The MAX97001 pulls down SDA during the entire master-generated 9th clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master retries communication. The master pulls down SDA during the 9th clock cycle to acknowledge receipt of data when the MAX97001 is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not-acknowledge is sent when the master reads the final byte of data from the MAX97001, followed by a STOP condition. Write Data Format A write to the MAX97001 includes transmission of a START condition, the slave address with the R/W bit set to 0, one byte of data to configure the internal register address pointer, one or more bytes of data, and a STOP condition. Figure 10 illustrates the proper frame format for writing one byte of data to the MAX97001. Figure 11 illustrates the frame format for writing n-bytes of data to the MAX97001. The slave address with the R/W bit set to 0 indicates that the master intends to write data to the MAX97001. The MAX97001 acknowledges receipt of the address byte during the master-generated 9th SCL pulse. The second byte transmitted from the master configures the MAX97001's internal register address pointer. The pointer tells the MAX97001 where to write the next byte of data. An acknowledge pulse is sent by the MAX97001 upon receipt of the address pointer data. The third byte sent to the MAX97001 contains the data that is written to the chosen register. An acknowledge pulse from the MAX97001 signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential registers within one continuous frame. The master signals the end of transmission by issuing a STOP condition. Register addresses greater than 0x09 are reserved. Do not write to these addresses.
MAX97001
START CONDITION SCL 1 28
CLOCK PULSE FOR ACKNOWLEDGMENT
9 NOT ACKNOWLEDGE
SDA ACKNOWLEDGE
Figure 9. Acknowledge
31
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers MAX97001
ACKNOWLEDGE FROM MAX97001 B7 ACKNOWLEDGE FROM MAX97001 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX97001 REGISTER ADDRESS A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P B6 B5 B4 B3 B2 B1 B0
Figure 10. Writing One Byte of Data to the MAX97001
ACKNOWLEDGE FROM MAX97001 ACKNOWLEDGE FROM MAX97001 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX97001 REGISTER ADDRESS A B7 B6 B5 B4 B3 B2 B1 B0 DATA BYTE 1 1 BYTE A
ACKNOWLEDGE FROM MAX97001 B7 B6 B5 B4 B3 B2 B1 B0 DATA BYTE n 1 BYTE A P
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 11. Writing n-Bytes of Data to the MAX97001
Read Data Format Send the slave address with the R/W bit set to 1 to initiate a read operation. The MAX97001 acknowledges receipt of its slave address by pulling SDA low during the 9th SCL clock pulse. A START command followed by a read command resets the address pointer to register 0x00. The first byte transmitted from the MAX97001 is the contents of register 0x00. Transmitted data is valid on the rising edge of SCL. The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read is from register 0x00. The address pointer can be preset to a specific register before a read command is issued. The master presets
the address pointer by first sending the MAX97001's slave address with the R/W bit set to 0 followed by the register address. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The MAX97001 then transmits the contents of the specified register. The address pointer autoincrements after transmitting the first byte. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figure 12 illustrates the frame format for reading one byte from the MAX97001. Figure 13 illustrates the frame format for reading multiple bytes from the MAX97001.
32
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers MAX97001
ACKNOWLEDGE FROM MAX97001 S SLAVE ADDRESS R/W 0 ACKNOWLEDGE FROM MAX97001 REGISTER ADDRESS A ACKNOWLEDGE FROM MAX97001 Sr SLAVE ADDRESS R/W 1 NOT ACKNOWLEDGE FROM MASTER
A
DATA BYTE 1 BYTE
A
P
REPEATED START
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 12. Reading One Byte of Data from the MAX97001
ACKNOWLEDGE FROM MAX97001 S SLAVE ADDRESS R/W 0
ACKNOWLEDGE FROM MAX97001 REGISTER ADDRESS A
ACKNOWLEDGE FROM MAX97001 Sr SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P
REPEATED START
Figure 13. Reading n-Bytes of Data from the MAX97001
Applications Information
Traditional Class D amplifiers require an output filter to recover the audio signal from the amplifier's output. The filters add cost, increase the solution size of the amplifier, and can decrease efficiency and THD+N performance. The traditional PWM scheme uses large differential output swings (2 x VDD(P-P)) and causes large ripple currents. Any parasitic resistance in the filter components results in a loss of power, lowering the efficiency. The MAX97001 does not require an output filter. The device relies on the inherent inductance of the speaker coil and the natural filtering of both the speaker and the human ear to recover the audio component of the square-wave output. Eliminating the output filter results in a smaller, less costly, more efficient solution. Because the frequency of the MAX97001 output is well beyond the bandwidth of most speakers, voice coil movement due to the square-wave frequency is very small. Although this movement is small, a speaker not designed to handle the additional power can be damaged. For optimum results, use a speaker with a series inductance > 10FH. Typical 8I speakers exhibit series inductances in the 20FH to 100FH range.
Filterless Class D Operation
GSM radios transmit using time-division multiple access (TDMA) with 217Hz intervals. The result is an RF signal with strong amplitude modulation at 217Hz and its harmonics that are easily demodulated by audio amplifiers. The MAX97001 is designed specifically to reject RF signals; however, PCB layout has a large impact on the susceptibility of the end product. In RF applications, improvements to both layout and component selection decreases the MAX97001's susceptibility to RF noise and prevent RF signals from being demodulated into audible noise. Trace lengths should be kept below 1/4 of the wavelength of the RF frequency of interest. Minimizing the trace lengths prevents them from functioning as antennas and coupling RF signals into the MAX97001. The wavelength (l) in meters is given by: l = c/f where c = 3 x interest. 108 m/s, and f = the RF frequency of
RF Susceptibility
Route audio signals on middle layers of the PCB to allow ground planes above and below to shield them from RF interference. Ideally, the top and bottom layers of the PCB should primarily be ground planes to create effective shielding.
33
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers
Additional RF immunity can also be obtained from relying on the self-resonant frequency of capacitors as it exhibits the frequency response similar to a notch filter. Depending on the manufacturer, 10pF to 20pF capacitors typically exhibit self resonance at RF frequencies. These capacitors when placed at the input pins can effectively shunt the RF noise at the inputs of the MAX97001. For these capacitors to be effective, they must have a lowimpedance, low-inductance path to the ground plane. Do not use microvias to connect to the ground plane as these vias do not conduct well at RF frequencies.
MAX97001
OUT+
MAX97001
OUT-
Figure 14. Optional Class D Ferrite Bead Filter
Component Selection
Optional Ferrite Bead Filter Additional EMI suppression can be achieved using a filter constructed from a ferrite bead and a capacitor to ground (Figure 14). Use a ferrite bead with low DC resistance, high-frequency (> 600MHz) impedance between 100I and 600I, and rated for at least 1A. The capacitor value varies based on the ferrite bead chosen and the actual speaker lead length. Select a capacitor less than 1nF based on EMI performance. Input Capacitor An input capacitor, CIN, in conjunction with the input impedance of the MAX97001 line inputs forms a highpass filter that removes the DC bias from an incoming analog signal. The AC-coupling capacitor allows the amplifier to automatically bias the signal to an optimum DC level. Assuming zero-source impedance, the -3dB point of the highpass filter is given by:
Charge-Pump Flying Capacitor The value of the flying capacitor (connected between C1N and C1P) affects the output resistance of the charge pump. A value that is too small degrades the device's ability to provide sufficient current drive, which leads to a loss of output voltage. Increasing the value of the flying capacitor reduces the charge-pump output resistance to an extent. Above 1FF, the on-resistance of the internal switches and the ESR of external chargepump capacitors dominate. Charge-Pump Holding Capacitor The holding capacitor (bypassing HPVDD and HPVSS) value and ESR directly affect the ripple on the supply. Increasing the capacitor's value reduces output ripple. Likewise, decreasing the ESR reduces both ripple and output resistance. Lower capacitance values can be used in systems with low maximum output power levels. See the Output Power vs. Load Resistance graph in the Typical Operating Characteristics for more information Supply Bypassing, Layout, and Grounding Proper layout and grounding are essential for optimum performance. Use a large continuous ground plane on a dedicated layer of the PCB to minimize loop areas. Connect GND directly to the ground plane using the shortest trace length possible. Proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any digital noise from coupling into the analog audio signals. Place the capacitor between C1P and C1N as close to the MAX97001 as possible to minimize trace length from C1P to C1N. Inductance and resistance added between C1P and C1N reduce the output power of the headphone amplifier. Bypass HPVDD and HPVSS with capacitors located close to the pins with a short trace length to GND. Close decoupling of HPVDD and HPVSS minimizes supply ripple and maximizes output power from the headphone amplifier.
f-3dB =
1 2RINCIN
Choose CIN such that f-3dB is well below the lowest frequency of interest. For best audio quality, use capacitors whose dielectrics have low-voltage coefficients, such as tantalum or aluminum electrolytic. Capacitors with highvoltage coefficients, such as ceramics, may result in increased distortion at low frequencies. Charge-Pump Capacitor Selection Use capacitors with an ESR less than 100mI for optimum performance. Low-ESR ceramic capacitors minimize the output resistance of the charge pump. Most surfacemount ceramic capacitors satisfy the ESR requirement. For best performance over the extended temperature range, select capacitors with an X7R dielectric.
34
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers
Bypass PVDD to GND with as little trace length as possible. Connect OUTP and OUTN to the speaker using the shortest and widest traces possible. Reducing trace length minimizes radiated EMI. Route OUTP/OUTN as a differential pair on the PCB to minimize the loop area thereby reducing the inductance of the circuit. If filter components are used on the speaker outputs, be sure to locate them as close as possible to the MAX97001 to ensure maximum effectiveness. Minimize the trace length from any ground tied passive components to GND to further minimize radiated EMI. An evaluation kit (EV kit) is available to provide an example layout for the MAX97001. The EV kit allows quick setup of the MAX97001 and includes easy-to-use software, allowing all internal registers to be controlled. WLP Applications Information For the latest application details on WLP construction, dimensions, tape carrier information, PCB techniques, bump-pad layout, and the recommended reflow temperature profile, as well as the latest information on reliability testing results, refer to the Application Note 1891: WaferLevel Packaging (WLP) and Its Applications on Maxim's website at www.maxim-ic.com/ucsp. See Figure 15 for the recommended PCB footprint for the MAX97001.
MAX97001
0.25mm
0.22mm
Figure 15. Recommended PCB Footprint
35
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifiers MAX97001
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages._Note that a "+", "#", or "-" in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE_TYPE 20 WLP PACKAGE_CODE W202A2+2 DOCUMENT_NO. 21-0059
20L WLP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
36_____________________ ________ Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c)
2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.

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